Christian
Schulte
Title:
VLSI yield optimization in detailed routing
Abstract:
A huge problem in today's VLSI chip production is the low
fraction of
actually functioning chips at the end of the production process - one
single dustparticle in the clean rooms can make a chip completely
unusable.
Therefore there is a high interest on methods that
consider yield already during the physical design phase of the chip. In
one of the last steps in the VLSI design process, the Routing, where
the task is to find disjoint connections between certain
pins of the chip, yield is heavily influenced by the density of the
resulting wiring.
We
describe an efficient, minimum cost flow based method which, given an
already routed design, optimizes yield by evenly distributing the wires
over the chip area while preserving all connections and respecting all
minimum distance constraints.